A complementary metal-oxide-semiconductor (CMOS) transistor can be modeled as a four-terminal (body, gate, source, and drain) device on a silicon substrate.
To turn off a “p-type” transistor and reduce unintended electrical currents, the gate terminal of the transistor may be biased with a voltage (“VG”) equal to or higher than the largest voltage between the transistor's source (“VS”) and drain (“VD”) voltages. Similarly, to avoid undesirable circuit behaviors due to accidentally forward-biased p-n junctions (e.g., latch-up), the body terminal of the transistor may also be biased with the greater of VS and VD. Hence, in situations where more than one supply voltage is available, a power monitor circuit may be used to determine the highest available voltage to properly bias these transistors.
As the inventors hereof have recognized, however, due to their high static power consumption, traditional power monitoring circuits are not suitable for use in low-power devices. The problem is compounded in situations where a single electronic device has several independently-powered domains, and therefore require a correspondingly large number of monitoring circuits. When employed in large numbers, the power consumption of monitoring circuits becomes even more significant.